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28F128J3A Datasheet(数据表) 5 Page - Intel Corporation

部件型号  28F128J3A
说明  3 Volt Intel StrataFlash Memory
下载  58 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
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28F128J3A Datasheet(HTML) 5 Page - Intel Corporation

 
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Preliminary
v
28F128J3A, 28F640J3A, 28F320J3A
Revision History
Date of Revision
Version
Description
07/07/99
-001
Original Version
08/03/99
-002
A0–A2 indicated on block diagram
09/07/99
-003
Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte
Mode currents. Modified RP# on AC Waveform for Write Operations
12/16/99
-004
Changed Block Erase time and tAVWH
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
03/16/00
-005
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter
table
Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed VOL of 0.45 V
Removed VOH of 2.4 V
Updated ICCR Typ values
Added Max lock-bit program and lock times
Added note on max measurements
06/26/00
-006
Updated cover sheet statement of 700 million units to one billion.
Corrected Table 10 to show correct maximum program times.
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
2/15/01
-007
Updated cover page to reflect 100K minimum erase cycles.
Updated cover page to reflect 110 ns 32M read speed.
Removed Set Read Configuration command from Table 4.
Updated Table 8 to reflect reserved bits are 1-7; not 2-7.
Updated Table 16 bit 2 definition from R to PSS.
Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Sec-
tion 6.5, AC Characteristics–Read-Only Operations (1,2)
Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section
6.6, AC Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75
µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per-
formance (1,2,3)
04/13/01
-008
Revised Section 7.0, Ordering Information




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