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28F128J3A 数据表(PDF) 34 Page - Intel Corporation |
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28F128J3A 数据表(HTML) 34 Page - Intel Corporation |
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34 / 58 page  28F128J3A, 28F640J3A, 28F320J3A 28 Preliminary device will latch in address and data and program the specified location. The allowable addresses are shown in Table 20 or Table 21. See Figure 14, “Protection Register Programming Flowchart” on page 37 Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error (program error bit SR.4 will be set to 1). Attempting to program a locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR.1 will be set to 1). 4.15.3 Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program “FFFD” to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible. 0667_06 NOTE: A0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing). For x8 mode A0 is used (See Table 21 for x8 addressing). Figure 6. Protection Register Memory Map 4 Words Factory Programmed 4 Words User Programmed 1 Word Lock 88H 85H 84H 81H 80H Word Address A[23 - 1]: 128 Mbit A[22 - 1]: 64 Mbit A[21 - 1]: 32 Mbit |
类似零件编号 - 28F128J3A |
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类似说明 - 28F128J3A |
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