数据搜索系统,热门电子元器件搜索 |
|
AD1868 数据表(PDF) 5 Page - Analog Devices |
|
AD1868 数据表(HTML) 5 Page - Analog Devices |
5 / 12 page AD1868 REV. A –5– 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 18-BIT DAC 18-BIT SERIAL REGISTER 18-BIT SERIAL REGISTER AD1868 LL DL CK DR LR DGND NRL AGND NRR VL VBR VBL VS VOL VOR VS 18-BIT DAC – + – + VREF VREF Functional Block Diagram ANALOG CIRCUIT CONSIDERATIONS GROUNDING RECOMMENDATIONS The AD1868 has two ground pins, designated as AGND (Pin 12) and DGND (Pin 7). The analog ground, AGND, serves as the “high quality” reference ground for analog signals and as a return path for the supply current from the analog portion of the device. The system analog common should be located as close as possible to Pin 12 to minimize any voltage drop which may develop between these two points, although the internal circuit is designed to minimize signal dependence of the analog return current. The digital ground, DGND, returns ground current from the digital logic portion of the device. This pin should be connected to the digital common node in the system. As shown in Figure 7, the analog and digital grounds should be joined at one point in the system. When these two grounds are remotely connected such as at the power supply ground, care should be taken to minimize the voltage difference between the DGND and AGND pins in order to ensure the specified performance. POWER SUPPLIES AND DECOUPLING The AD1868 has three power supply input pins. VS (Pins 9 and 15) provides the supply voltages which operate the analog por- tion of the device including the 18-bit DACs, the voltage refer- ences, and the output amplifiers. The VS supplies are designed to operate with a +5 V supply. These pins should be decoupled to analog common using a 0.1 µF capacitor. Good engineering practice suggests that the bypass capacitors be placed as close as possible to the package pins. This minimizes the inherent induc- tive effects of printed circuit board traces. VL (Pin 1) operates the digital portions of the chip including the input shift registers and the input latching circuitry. VL is also designed to operate with a +5 V supply. This pin should be by- passed to digital common using a 0.1 µF capacitor, again placed as close as possible to the package pin. Figure 7 illustrates the cor- rect connection of the digital and analog supply bypass capacitors. An important feature of the AD1868 audio DAC is its ability to operate at reduced power supply voltages. This feature is very important in portable battery operated systems. As the batteries discharge, the supply voltage drops. Unlike any other audio DAC, the AD1868 can continue to function at supply voltages as low as 3.5 V. Because of its unique design, the power require- ments of the AD1868 diminish as the battery voltage drops, fur- ther extending the operating time of the system. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 LL DL CK DR LR DGND NRL AGND NRR VL VBR VBL VS VOL VOR AD1868 POWER SUPPLY 0.1µF 0.1µF 4.7µF 4.7µF VS Figure 7. Recommended Circuit Schematic NOISE REDUCTION CAPACITORS The AD1868 has two noise reduction pins designated as NRL (Pin 13) and NRR (Pin 11). It is recommended that external noise reduction capacitors be connected from these pins to AGND to reduce the output noise contributed by the voltage reference circuitry. As shown in Figure 7, each of these pins should be bypassed to AGND with a 4.7 µF or larger capacitor. The connections between the capacitors, package pins and AGND should be as short as possible to achieve the lowest noise. USING VBL AND VBR The AD1868 has two bias voltage reference pins, designated as VBR (Pin 8) and VBL (Pin 16). These pins supply a dc reference voltage equal to the center of the output voltage swing. These bias voltages replace “False Ground” networks previously required in single-supply audio systems. At the same time, they allow dc- coupled systems, improving audio performance. Figure 8a illustrates the traditional approach used to generate False Ground voltages in single-supply audio systems. This cir- cuit requires additional power and circuit board space. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-BIT LATCH 16-BIT DAC SERIAL INPUT REGISTER CONTROL LOGIC AD1851 IOUT –VS DGND NC CLK LE DATA +VL NC = NO CONNECT +VS TRIM MSB ADJ IOUT AGND SJ RF VOUT NC Figure 8a. Schematic Using False Ground |
类似零件编号 - AD1868_15 |
|
类似说明 - AD1868_15 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |