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AD872A 数据表(PDF) 4 Page - Analog Devices |
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AD872A 数据表(HTML) 4 Page - Analog Devices |
4 / 20 page REV. A –4– AD872A SWITCHING SPECIFICATIONS Parameter Symbol J, S Grades Units Clock Period1 tC 100 ns min CLOCK Pulsewidth High tCH 45 ns min CLOCK Pulsewidth Low tCL 45 ns min Clock Duty Cycle2 40 % min (50% typ) 60 % max Output Delay tOD 10 ns min (20 ns typ) Pipeline Delay (Latency) 3 Clock Cycles Data Access Time (LCC Package Only)2 tDD 50 ns typ (100 pF Load) Output Float Delay (LCC Package Only)2 tHL 50 ns typ (10 pF Load) NOTES 1Conversion rate is operational down to 10 kHz without degradation in specified performance. 2See section on Three-State Outputs for timing diagrams and applications information. Specifications subject to change without notice. CLOCK N+1 DATA N DATA N+1 VIN N N N+1 t OD t C BIT 2–12 MSB, OTR t CH t CL Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS 1 Parameter With Respect to Min Max Units AVDD AGND –0.5 +6.5 Volts AVSS AGND –6.5 +0.5 Volts DVDD, DRVDD 2 DGND, DRGND2 –0.5 +6.5 Volts DRVDD 2 DVDD –6.5 +6.5 Volts DRGND DGND –0.3 +0.3 Volts AGND DGND –1.0 +1.0 Volts AVDD DVDD –6.5 +6.5 Volts Clock Input, OEN2 DGND –0.5 DVDD + 0.5 Volts Digital Outputs DGND –0.5 DVDD + 0.3 Volts VINA, VINB, REF IN AGND –6.5 +6.5 Volts REF IN AGND AVSS AVDD Volts Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2LCC package only. (TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V; VIL = 0.8 V, VIN = 2.0 V, VOL = 0.4 V and VOH = 2.4 V) |
类似零件编号 - AD872A_15 |
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类似说明 - AD872A_15 |
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