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GMS81608TPL 数据表(PDF) 41 Page - Hynix Semiconductor |
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GMS81608TPL 数据表(HTML) 41 Page - Hynix Semiconductor |
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41 / 79 page  INTERRUPTS The GMS81604/08 interrupt circuits consist of Inter- rupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, priority circuit and Master en- able flag(I flag of PSW). The configuration of interrupt circuit is shown in Figure 28. 12 interrupt sources are provided including the Reset. Interrupt source Symbol Priority Hardware RESET External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 AD Converter Watch dog timer Basic interval timer RST INT0IF INT1IF INT2IF INT3IF T0IF T1IF T2IF T3IF AIF WDTIF BITIF 1 2 3 4 5 6 7 8 9 10 11 12 *Vector addresses are shown in Program Memory section. The External Interrupts INT0~INT3 can each be tran- sition-activated, depending on interrupt edge selection register. The Timer 0~Timer 3 Interrupts are generated by T0IF ~T3IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by AIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer/counter register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 29. These registers are composed of interrupt enable flags of each interrupt source, these flags determines INT0IF INT1IF INT2IF INT3IF T0IF T1IF T2IF T3IF AIF WDTIF BITIF PRIORITY CONTROL INT2 RESET BRK (Software Interrupt) I-FLAG 1 0 I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. IENH IENL IRQH IRQL INT1 INT0 INT3 TIMER 0 TIMER 1 TIMER 2 TIMER 3 ADC WDT BASIC INTERVAL TIMER TO CPU MSB LSB BIT 7 BIT 6 BIT 5 RELEASE THE STOP (IF IN STOP MODE) Master Enable Flag 0 1 Figure 28. Block Diagram of Interrupt Function LG Semicon GMS81604/08 37 |
类似零件编号 - GMS81608TPL |
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类似说明 - GMS81608TPL |
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