©1993 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74VHC373 Rev. 1.3

2

Logic Symbol

IEEE/IEC

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

Z

= High Impedance

X

= Immaterial

Latch Enable

Functional Description

The

VHC373

contains

eight

D-type

latches

with

3-STATE standard outputs. When the Latch Enable (LE)

In this condition the latches are transparent, i.e., a latch

output will change state each time its D input changes.

When LE is LOW, the latches store the information that

was present on the D inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE standard

outputs are controlled by the Output Enable (OE) input.

When OE is LOW, the standard outputs are in the

2-state mode. When OE is HIGH, the standard outputs

are in the high impedance mode but this does not inter-

fere with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Figure 1.

Inputs

Outputs

LE

OE

XHX

Z

HL

L

L

HLH

H

LL

X