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74F138PC 数据表(PDF) 2 Page - Fairchild Semiconductor

部件名 74F138PC
功能描述  1-of-8 Decoder/Demultiplexer
Download  7 Pages
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

74F138PC 数据表(HTML) 2 Page - Fairchild Semiconductor

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2
Unit Loading/Fan Out
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Functional Description
The
F138
high-speed
1-of-8
decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and,
when enabled, provides eight mutually exclusive active
LOW outputs (O0–O7). The F138 features three Enable
inputs, two active LOW (E1, E2) and one active HIGH (E3).
All outputs will be HIGH unless E1 and E2 are LOW and E3
is HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four F138 devices and one inverter (See
Figure 1). The F138 can be used as an 8-output demulti-
plexer by using one of the active LOW Enable inputs as the
data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active HIGH or active LOW state.
FIGURE 1. Expansion to 1-of-32 Decoding
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
A0–A2
Address Inputs
1.0/1.0
20
µA/−0.6 mA
E1, E2
Enable Inputs (Active LOW)
1.0/1.0
20
µA/−0.6 mA
E3
Enable Input (Active HIGH)
1.0/1.0
20
µA/−0.6 mA
O0–O7
Outputs (Active LOW)
50/33.3
−1 mA/20 mA
Inputs
Outputs
E1
E2
E3
A0
A1
A2
O0
O1
O2
O3
O4
O5
O6
O7
H
XXXXX
H
H
H
HHHHH
X
H
XXXX
H
H
H
HHHHH
X
X
L
X
X
X
HH
H
HHHHH
LL
H
LLLL
H
H
HHHHH
L
L
HH
L
L
H
L
H
HHHHH
L
L
H
L
H
L
HH
L
HHHHH
L
L
HHH
L
H
H
H
L
HHHH
L
L
H
L
L
HHH
H
H
L
HHH
L
L
HH
L
HHH
H
H
H
L
HH
L
L
H
L
HHHH
H
HHH
L
H
L
L
HHHHHH
H
HHHH
L


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