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ADC108S022 数据表(PDF) 5 Page - Texas Instruments |
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ADC108S022 数据表(HTML) 5 Page - Texas Instruments |
5 / 25 page ADC108S022 www.ti.com SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 ADC108S022 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (2) VA = VD = +2.7V to +3.6V, 0.36 0.94 mA (max) fSAMPLE = 200 kSPS, fIN = 40 kHz Total Supply Current Normal Mode ( CS low) VA = VD = +4.75V to +5.25V, 1.28 2.1 mA (max) fSAMPLE = 200 kSPS, fIN = 40 kHz IA + ID VA = VD = +2.7V to +3.6V, 30 nA fSCLK = 0 ksps Total Supply Current Shutdown Mode (CS high) VA = VD = +4.75V to +5.25V, 60 nA fSCLK = 0 ksps VA = VD = +3.0V 1.1 2.8 mW (max) fSAMPLE = 200 kSPS, fIN = 40 kHz Power Consumption Normal Mode ( CS low) VA = VD = +5.0V 6.4 10.5 mW (max) fSAMPLE = 200 kSPS, fIN = 40 kHz PC VA = VD = +3.0V 0.09 µW fSCLK = 0 ksps Power Consumption Shutdown Mode (CS high) VA = VD = +5.0V 0.30 µW fSCLK = 0 ksps AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum Clock Frequency 0.8 MHz (min) fSCLK Maximum Clock Frequency 16 3.2 MHz (max) 50 ksps (min) Sample Rate fS Continuous Mode 1000 200 ksps (max) tCONVERT Conversion (Hold) Time 13 SCLK cycles 30 40 % (min) DC SCLK Duty Cycle 70 60 % (max) tACQ Acquisition (Track) Time 3 SCLK cycles Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles tAD Aperture Delay 4 ns ADC108S022 Timing Specifications The following specifications apply for VA = VD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (1) tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min) CS Setup Time prior to SCLK Rising tCSS 5 10 ns (min) Edge tEN CS Falling Edge to DOUT enabled 5 30 ns (max) DOUT Access Time after SCLK Falling tDACC 17 27 ns (max) Edge DOUT Hold Time after SCLK Falling tDHLD 4 ns (typ) Edge DIN Setup Time prior to SCLK Rising tDS 3 10 ns (min) Edge tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min) tCH SCLK High Time 0.4 x tSCLK ns (min) tCL SCLK Low Time 0.4 x tSCLK ns (min) (1) Tested limits are specified to AOQL (Average Outgoing Quality Level). Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC108S022 |
类似零件编号 - ADC108S022 |
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类似说明 - ADC108S022 |
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