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DESCRIPTION

TSB12LV21B

TSB12LV21BI

TSB12LV21BM

SLLA213 – JUNE 2006

(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER

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Supports Plug-and-Play (PnP) Specification

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IEEE Standard for 1394-1995 Compliant

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Generates 32-bit CRC for Transmission of

1394 Packets

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IEEE Standard for 1212-1991 Compliant

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Performs 32-bit CRC Checking on Reception

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Supports IEEE 1394-1995 Link Layer Control

of 1394 Packets

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PCI Local Bus Specification Rev. 2.1

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Provides PCI Bus Master Function for

Compliant

Supporting DMA Operations

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Supports IEEE 1394 Transfer Rates of 100,

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Provides PCI Slave Function for Read/Write

200, and 400 Mb per Second

Access of Internal Registers

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3.3-V Core Logic While Maintaining 5-V

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Supports Distributed DMA Transfers Between

Tolerant Inputs

1394 and Local Bus RAM, ROM, AUX, or

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Performs the Function of 1394 Cycle Master

Zoomed Video

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Provides 4K Bytes of Configurable FIFO RAM

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Advanced Submicron, Low-Power CMOS

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Provides Five Scatter-Gather DMA Channels

Technology

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Provides Software Control of Interrupt Events

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Packaged in a 176-Pin PQFP (PGF)

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Provides Four General-Purpose

Input/Outputs

The TSB12LV21B (PCILynx-2) provides a high-performance IEEE 1394-1995 interface with the capability to

transfer data between the 1394 PHY-link interface, the PCI bus interface, and external devices connected to the

local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical layer device; it is

supported by the onboard link layer controller (LLC). The LLC provides the control for transmitting and receiving

1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s.

The link layer also provides the capability to receive status from the physical layer device and to access the

physical layer control and status registers by the application software. The PCILynx–2 complies with

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PCI Local Bus Specification, Revision 2.1

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IEEE Standard for a 1394-1995 High Performance Serial Bus

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IEEE Standard 1212-1991

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IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses

An internal 4Kbyte-memory can be configured as multiple variable-size FIFOs, eliminating the need for external

FIFOs. Separate FIFOs are user configurable to support 1394 receive, asynchronous transmit, and

isosynchronous transmit transfer operations.

The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating both as a master and

as a target device. Configuration registers can be loaded from an external serial EEPROM, allowing board and

system designers to assign their own unique identification codes. An autoboot mode allows data-moving

systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.

The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the

DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is

connected to a local bus port. The PCLs implement an instruction set that allows linking, conditional branching,

1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels accommodate

programmable data types. PCLs can be chained together to form a channel control program that can be

developed to support each DMA channel. Data can be stored in either big endian or little endian format,

eliminating the need for the host CPU to perform byte swapping. Data can be transferred either to 4-byte aligned

locations, to provide the highest performance, or to nonaligned locations, to provide the best memory use.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.