TSB43EC42

M6

External CPU or

PCI Interface

Async RX FIFO

MPEG2 Demux and Decode

MPEG2

Transport Stream

SDRAM

CPU

PCI or68 K Bus

Graphics

Controller

Video

NTSC/PAL

Encoder

Display

Audio DAC

(2 channel

audio)

Speaker

1394

Bus

TSB43Ex4x

www.ti.com

SLLA275C – APRIL 2008 – REVISED FEBRUARY 2010

APPLICATION INFORMATION

In an HDTV application (see Figure 1), the TSB43EC42/43 receives the MPEG2 transport stream, decrypts it

using the M6 cipher, and outputs it to the application over the HSDI port AES encrypted. The MPEG2 demux and

decode device separates the audio and video streams, decodes them, and outputs the 2-channel audio to an

audio DAC for listening and the video to an NTSC/PAL encoder for display.

The HDTV receives on-screen display (OSD) information from the video source, such as a set-top box, using the

EIA775 standard. The system processor receives the OSD data through the TSB43EC42/43 asynchronous

receive buffer. The system graphics controller controls the OSD and mixes it with the video data for display.

Figure 1. TSB43EC42/43 in HDTV Application

Copyright © 2008–2010, Texas Instruments Incorporated

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