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LM3502 数据表(PDF) 2 Page - Texas Instruments

部件名 LM3502
功能描述  Step-Up Converter for White LED Applications
Download  28 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

LM3502 数据表(HTML) 2 Page - Texas Instruments

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A1
A2
A3
B1
B3
C1
C3
D1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LM3502
SNVS339A – SEPTEMBER 2005 – REVISED AUGUST 2006
www.ti.com
Connection Diagrams
Figure 2. TOP VIEW
Figure 3. TOP VIEW
10-Bump Thin DSBGA
16-Lead Thin WQFN
See Package Number (YPA0010)
See Package Number (RGH0016A)
PIN DESCRIPTIONS
Bump #
Pin #
Name
Description
A1
9
Cntrl
Shutdown Control Connection
B1
7
Fb
Feedback Voltage Connection
C1
6
VOUT2
Drain Connections of The NMOS and PMOS Field Effect Transistor (FET) Switches (Figure 4: N2
and P1)
D1
4
VOUT1
Over-Voltage Protection (OVP) and Source Connection of The PMOS FET Switch (Figure 4: P1)
D2
2 and 3
Sw
Drain Connection of The Power NMOS Switch (Figure 4: N1)
D3
15 and 16
PGND
Power Ground Connection
C3
14
AGND
Analog Ground Connection
B3
13
VIN
Supply or Input Voltage Connection
A3
12
En2
NMOS FET Switch Control Connection
A2
10
En1
PMOS FET Switch Control Connection
1
NC
No Connection
5
NC
No Connection
8
NC
No Connection
11
NC
No Connection
DAP
DAP
Die Attach Pad (DAP), must be soldered to the printed circuit board’s ground plane for enhanced
thermal dissipation.
Cntrl (Bump A1): Shutdown control pin
When VCntrl is ≥ 1.4V, the LM3502 is enabled or ON. When VCntrl is ≤ 0.3V, the LM3502 will
enter into shutdown mode operation. The LM3502 has an internal pull down resistor on the
Cntrl pin, thus the device is normally in the off state or shutdown mode of operation.
Fb (Bump B1): Output voltage feedback connection
The white LED string network current is set/programmed using a resistor from this pin to
ground.
VOUT2 (Bump C1): Drain connections of the internal PMOS and NMOS FET switches
. (Figure 4: P1 and N2). It is recommended to connect 100nF at VOUT2 for the LM3502-35V
and LM3502-44 versions if VOUT2 is not used.
VOUT1 (Bump D1): Source connection of the internal PMOS FET switch (Figure 4: P1) and OVP sensing node
The output capacitor must be connected as close to the device as possible, between the
VOUT1 pin and ground plane. Also connect the Schottky diode as close as possible to the
2
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM3502


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