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SI3018 数据表(PDF) 11 Page - List of Unclassifed Manufacturers |
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SI3018 数据表(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 94 page Si3056 Si3018/19/10 Rev. 1.05 11 Figure 3. Serial Interface Timing Diagram (DCE = 0) Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0) (VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL =20pF) Parameter Symbol Min Typ Max Unit Cycle time, SCLK tc 244 1/256 Fs — ns SCLK Duty Cycle tdty —50 — % Delay Time, SCLK ↑ to FSYNC↓ td1 —— 20 ns Delay Time, SCLK ↑ to SDO Valid td2 —— 20 ns Delay Time, SCLK ↑ to FSYNC↑ td3 —— 20 ns Setup Time, SDI Before SCLK ↓ tsu 25 — — ns Hold Time, SDI After SCLK ↓ th 20 — — ns Setup Time, FC ↑ Before SCLK↑ tsfc 40 — — ns Hold time, FC ↑ After SCLK↑ thfc 40 — — ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VD – 0.4 V, VIL =0.4 V. D15 SCLK t c t d1 V OH V OL FSYNC (mode 0) FSYNC (mode 1) t d3 t d3 16-Bit SDO 16-Bit SDI D14 D1 D0 D0 D1 D14 D15 t su t h t sfc t hfc FC t d2 D0 |
类似零件编号 - SI3018 |
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类似说明 - SI3018 |
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