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AD7302BNZ 数据表(PDF) 3 Page - Analog Devices |
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AD7302BNZ 数据表(HTML) 3 Page - Analog Devices |
3 / 16 page AD7302 –3– REV. 0 TIMING CHARACTERISTICS1, 2 Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments t1 0 ns min Address to Write Setup Time t2 0 ns min Address Valid to Write Hold Time t3 0 ns min Chip Select to Write Setup Time t4 0 ns min Chip Select to Write Hold Time t5 20 ns min Write Pulse Width t6 15 ns min Data Setup Time t7 4.5 ns min Data Hold Time t8 20 ns min Write to LDAC Setup Time t9 20 ns min LDAC Pulse Width t10 20 ns min CLR Pulse Width NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2. tr and tf should not exceed 1 µs on any digital input. 2See Figure 1. A/B CS WR D7–D0 LDAC CLR t1 t2 t4 t3 t5 t6 t7 t8 t10 t9 Figure 1. Timing Diagram for Parallel Data Write (VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference; all specifications TMIN to TMAX unless otherwise noted) |
类似零件编号 - AD7302BNZ |
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类似说明 - AD7302BNZ |
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