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FM3164 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 FM3164
功能描述  64-Kbit/256-Kbit Integrated Processor Companion with F-RAM
Download  33 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

FM3164 数据表(HTML) 5 Page - Cypress Semiconductor

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FM3164/FM31256
Document Number: 001-86391 Rev. *C
Page 5 of 33
Overview
The FM3164/FM31256 device combines a serial nonvolatile
RAM with a real time clock (RTC) and a processor companion.
The companion is a highly integrated peripheral including a
processor supervisor, a comparator used for early power-fail
warning, nonvolatile event counters, and a 64-bit serial number.
The FM3164/FM31256 integrates these complementary but
distinct functions under a common interface in a single package.
The product is organized as two logical devices. The first is a
memory and the second is the companion which includes all the
remaining functions. From the system perspective they appear
to be two separate devices with unique IDs on the serial bus.
The memory is organized as a standalone nonvolatile I2C
memory using standard device ID value. The real time clock and
supervisor functions are accessed with a separate I2C device ID.
This allows clock/calendar data to be read while maintaining the
most recently used memory address. The clock and supervisor
functions are controlled by 25 special function registers. The
RTC and event counter circuits are maintained by the power
source on the VBAK pin, allowing them to operate from battery or
backup capacitor power when VDD drops below a set threshold.
Each functional block is described below.
Memory Architecture
The FM3164/FM31256 device is available in memory size
64-Kbit/256-Kbit. The device uses two-byte addressing for the
memory portion of the chip. This makes the device software
compatible with its standalone memory counterparts, but makes
them compatible within the entire family.
The memory array is logically organized as 8,192 × 8 bits /
32,768 × 8 bits and is accessed using an industry-standard I2C
interface. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or written at the
speed of the I2C bus with no delays for write operations. It also
offers effectively unlimited write endurance unlike other
nonvolatile memory technologies. The I2C protocol is described
on page 19.
The memory array can be write-protected by software. Two bits
in the processor companion area (WP1, WP0 in register 0Bh)
control the protection setting. Based on the setting, the protected
addresses cannot be written and the I2C interface will not
acknowledge any data to protected addresses. The special
function registers containing these bits are described in detail
below.
Processor Companion
In
addition
to
nonvolatile
RAM,
the
FM3164/FM31256
incorporates a real time clock and highly integrated processor
companion. The companion includes a low-VDD reset, a
programmable
watchdog
timer,
a
battery-backed
event
counters, a comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic functions:
detection of power supply fault conditions and a watchdog timer
to escape a software lockup condition. The FM3164/FM31256
has a reset pin (RST) to drive a processor reset input during
power faults, power-up, and software lockups. It is an open drain
output with a weak internal pull-up to VDD. This allows other reset
sources to be wire-OR'd to the RST pin. When VDD is above the
programmed trip point, RST output is pulled weakly to VDD. If
VDD drops below the reset trip point voltage level (VTP), the RST
pin will be driven LOW. It will remain LOW until VDD falls too low
for circuit operation which is the VRST level. When VDD rises
again above VTP, RST continues to drive LOW for at least
100 ms (tRPU) to ensure a robust system reset at a reliable VDD
level. After tRPU has been met, the RST pin will return to the weak
HIGH state. While RST is asserted, serial bus activity is locked
out even if a transaction occurred as VDD dropped below VTP. A
memory operation started while VDD is above VTP will be
completed internally.
Table 1 below shows how bits VTP(1:0) control the trip point of
the low-VDD reset. They are located in register 0Bh, bits 1 and 0.
The reset pin will drive LOW when VDD is below the selected VTP
voltage, and the I2C interface and F-RAM array will be locked
out. Figure 2 illustrates the reset operation in response to a low
VDD.
A watchdog timer can also be used to drive an active reset signal.
The watchdog is a free-running programmable timer. The
timeout period can be software programmed from 100 ms to 3
Table 1. Block Memory Write Protection
WP1
WP0
Protected Address Range
0
0
None
0
1
Bottom 1/4
1
0
Bottom 1/2
11
Full array
Table 2. VTP setting
VTP Setting
VTP1
VTP0
2.6 V
0
0
2.9 V
0
1
3.9 V
1
0
4.4 V
1
1
Figure 2. Low VDD Reset
VDD
VTP
tRPU
RST


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