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EP2SGX90E 数据表(PDF) 45 Page - Altera Corporation |
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EP2SGX90E 数据表(HTML) 45 Page - Altera Corporation |
45 / 326 page Altera Corporation 2–27 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture Figure 2–21. 8B/10B Decoder The 8B/10B decoder in single-width mode translates the 10-bit encoded data into the 8-bit equivalent data or control code. The 10-bit code received must be from the supported Dx.y or Kx.y list with the proper disparity or error flags asserted. All 8B/10B control signals, such as disparity error or control detect, are pipelined with the data and edge-aligned with the data. Figure 2–22 shows how the 10-bit symbol is decoded in the 8-bit data + 1-bit control indicator. Figure 2–22. 8B/10B Decoder Conversion The 8B/10B decoder in double-width mode translates the 20-bit (2 × 10-bits) encoded code into the 16-bit (2 × 8-bits) equivalent data or control code. The 20-bit upper and lower symbols received must be from the supported Dx.y or Kx.y list with the proper disparity or error flags 8B/10B Decoder MSByte datain[19..10] To Byte Deserializer dataout[15..8] Status Signals[1] (1) 8B/10B Decoder LSByte datain[9..0] dataout[7..0] Status Signals[0] From Rate Matcher (1) 98 76 5 4 3 2 1 0 8B/10B conversion jh g f i e d c b a MSB received last LSB received first 76 5 4 3 2 1 0 HG F E D C B A + ctrl Parallel data |
类似零件编号 - EP2SGX90E |
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类似说明 - EP2SGX90E |
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