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EP2SGX30D 数据表(PDF) 94 Page - Altera Corporation |
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EP2SGX30D 数据表(HTML) 94 Page - Altera Corporation |
94 / 326 page 2–76 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 TriMatrix Memory Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M-RAM block registers (renwe, address, byte enable, datain, and output registers). The output register can be bypassed. The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b , renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–53. Figure 2–53. M-RAM Block Control Signals The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right or left side drive the M-RAM block local interconnect. Up to 16 direct link input connections to the M-RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M-RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2–54 shows an example floorplan for the EP2SGX130 device and the location of the M-RAM interfaces. Figures 2–55 and 2–56 show the interface between the M-RAM block and the logic array. clock_a clock_b clocken_a clocken_b aclr_a aclr_b Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect renwe_a renwe_b 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect |
类似零件编号 - EP2SGX30D |
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类似说明 - EP2SGX30D |
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