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EP2SGX60C 数据表(PDF) 56 Page - Altera Corporation |
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EP2SGX60C 数据表(HTML) 56 Page - Altera Corporation |
56 / 326 page 2–38 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 Transceivers Figure 2–31. Stratix II GX Receiver PLL Recovered Clock to Regional Clock Connection Notes (1), (2) Notes to Figure 2–31: (1) CLK# pins are clock pins and their associated number. These are pins for global and local clocks. (2) R CLK# pins are regional clock pins. RCLK [3..0] RCLK [7..4] RCLK [23..20] RCLK [19..16] RCLK [11..8] RCLK [15..12] RCLK [31..28] RCLK [27..24] Stratix II GX Transceiver Block Stratix II GX Transceiver Block 12 6 11 5 CLK[7..4] CLK[15..12] CLK[3..0] 1 7 2 8 |
类似零件编号 - EP2SGX60C |
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类似说明 - EP2SGX60C |
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