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EP2AGX125 数据表(PDF) 89 Page - Altera Corporation |
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EP2AGX125 数据表(HTML) 89 Page - Altera Corporation |
89 / 380 page Chapter 4: DSP Blocks in Arria II Devices 4–13 DSP Block Resource Descriptions December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration 1 You can use the rounding and saturation logic units together or independently. Second Adder and Output Registers The second adder register and output register banks are two banks of 44-bit registers that you can combine to form larger 72-bit banks to support 36 × 36 output results. The outputs of the different stages in the Arria II devices are routed to the output registers through an output selection unit. Depending on the operational mode of the DSP block, the output selection unit selects whether the outputs of the DSP blocks come from the outputs of the multiplier block, first-stage adder, pipeline registers, second-stage adder, or the rounding and saturation logic unit. Based on the DSP block operational mode you specify, the output selection unit is automatically set by the software, and has the option to either drive or bypass the output registers. The exception is when the block is used in shift mode, where you dynamically control the output-select multiplexer directly. When the DSP block is configured in chained cascaded output mode, both of the second-stage adders are used. The first adder is for performing a four-multiplier adder and the second is for the chainout adder. The outputs of the four-multiplier adder are routed to the second-stage adder registers before enters the chainout adder. The output of the chainout adder goes to the regular output register bank. Depending on the configuration, you can route the chainout results to the input of the next half block’s chainout adder input or to the general fabric (functioning as regular output registers). You can only connect the chainin port to the chainout port of the previous DSP block and must not be connected to general routings. The second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. The clock[3..0], ena[3..0], and aclr[3..0] DSP block signals control the output registers in the DSP block. |
类似零件编号 - EP2AGX125 |
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类似说明 - EP2AGX125 |
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