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EP2AGX65 数据表(PDF) 13 Page - Altera Corporation |
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EP2AGX65 数据表(HTML) 13 Page - Altera Corporation |
13 / 380 page December 2013 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration Section I. Device Core for Arria II Devices This section provides a complete overview of all features relating to the Arria® II device family, the industry’s first cost-optimized 40 nm FPGA family. This section includes the following chapters: ■ Chapter 1, Overview for the Arria II Device Family ■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Arria II Devices ■ Chapter 3, Memory Blocks in Arria II Devices ■ Chapter 4, DSP Blocks in Arria II Devices ■ Chapter 5, Clock Networks and PLLs in Arria II Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. |
类似零件编号 - EP2AGX65 |
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类似说明 - EP2AGX65 |
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