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EP2AGX45 数据表(PDF) 16 Page - Altera Corporation

部件名 EP2AGX45
功能描述  Device Interfaces and Integration
Download  380 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP2AGX45 数据表(HTML) 16 Page - Altera Corporation

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Chapter 1: Overview for the Arria II Device Family
Arria II Device Feature
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012
Altera Corporation
Complete PIPE protocol solution with an embedded hard IP block that provides
physical interface and media access control (PHY/MAC) layer, Data Link layer,
and Transaction layer functionality
Optimized for high-bandwidth system interfaces
Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a
wide range of single-ended and differential I/O standards
High-speed LVDS I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to
1.25 Gbps
Low power
Architectural power reduction techniques
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps.
Power optimizations integrated into the Quartus II development software
Advanced usability and security features
Parallel and serial configuration options
On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration
for single-ended I/Os and on-chip differential (RD) termination for differential
I/O
256-bit advanced encryption standard (AES) programming file encryption for
design security with volatile and non-volatile key storage options
Robust portfolio of IP for processing, serial protocols, and memory interfaces
Low cost, easy-to-use development kits featuring high-speed mezzanine
connectors (HSMC)
Emulated LVDS output support with a data rate of up to 1152 Mbps


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