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CDCV850IDGGG4 数据表(PDF) 7 Page - Texas Instruments

部件名 CDCV850IDGGG4
功能描述  2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCV850IDGGG4 数据表(HTML) 7 Page - Texas Instruments

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CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of operating free-air temperature (unless
otherwisw noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpd
Propagation delay time
Test mode/CLK to any output
4
ns
tPHL
High-to low-level propagation delay time
SCLK to SDATA (acknowledge)
500{
ns
ten
Output enable time
Test mode/SDATA to Y-output
85
ns
tdis
Output disable time
Test mode/SDATA to Y-output
35
ns
tjit(per)
Jitter (period), See Figure 6
100/133 MHz
−30
30
ps
tjit(cc)
Jitter (cycle-to-cycle), See Figure 3
100/133 MHz
−30
30
ps
tjit(hper)
Half-period jitter, See Figure 7
100/133 MHz
−75
75
ps
100 MHz/VID on CLK = 0.71 V}
−120
120
0°C to 85°C
100 MHz/VID on CLK = 0.59 Vw
−50
160
ps
0°C to 85°C
100 MHz/VID on CLK = 0.82 VW
−170
70
ps
t
Static phase offset See Figure 4a
133 MHz/VID on CLK = 0.71 VW
−50
180
t(∅)
Static phase offset, See Figure 4a
100 MHz/VID on CLK = 0.71 V}
−160
80
40°C to 85°C
100 MHz/VID on CLK = 0.59 Vw
−90
120
ps
−40°C to 85°C
100 MHz/VID on CLK = 0.82 VW
−210
30
ps
133 MHz/VID on CLK = 0.71 VW
−80
150
Dynamic phase offset, SSC on, See Figure 4b and 100 MHz/VID on CLK = 0.71 V}
−190
190
ps
td #
Dynamic phase offset, SSC on, See Figure 4b and
Figure 9
133 MHz/VID on CLK = 0.71 V}
−140
140
ps
td(∅)#
Dynamic phase offset SSC off See Figure 4b
100 MHz/VID on CLK = 0.71 V}
−160
160
ps
Dynamic phase offset, SSC off, See Figure 4b
133 MHz/VID on CLK = 0.71 V}
−130
130
ps
tslr(o)
Output clock slew rate, terminated with
120Ω/14 pF, See Figures 1 and 8
1
2
V/ns
tslr(o)
Output clock slew rate, terminated with 120Ω/4 pF,
See Figures 1 and 8
1
3
V/ns
tsk(o)⏐⏐
Output skew, See Figure 5
75
ps
SSC modulation frequency
30
33.3
kHz
SSC clock input frequency deviation
0.00
−0.50
%
This time is for a PLL frequency of 100 MHz.
According CK00 spec: 6 x Iref at 50 Ω and Rref = 475 Ω
§ According CK00 spec: 5 x Iref at 50 Ω and Rref = 475 Ω
According CK00 spec: 7 x Iref at 50 Ω and Rref = 475 Ω
# The parameter is assured by design but cannot be 100% production tested.
|| All differential output pins are terminated with 120 Ω/4 pF


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