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CDCV850DGGG4 数据表(PDF) 3 Page - Texas Instruments |
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CDCV850DGGG4 数据表(HTML) 3 Page - Texas Instruments |
3 / 20 page CDCV850 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AGND 17 Ground for 2.5 -V analog supply AVDD 16 2.5 -V analog supply CLK, CLK 13, 14 I Differential clock input FBIN, FBIN 35, 36 I Feedback differential clock input FBOUT, FBOUT 32, 33 O Feedback differential clock output GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground SCLK 12 I Clock input for 2-line serial interface SDATA 37 I/O Data input/output for 2-line serial interface VDDQ 4, 11, 21, 28, 34, 38, 45 2.5-V supply VDDI 15 I 2.5-V or 3.3-V supply for 2-line serial interface Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 O Buffered output copies of input clock, CLK Y[0:9] 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 O Buffered output copies of input clock, CLK |
类似零件编号 - CDCV850DGGG4 |
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类似说明 - CDCV850DGGG4 |
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