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FAN4803CP-1 Datasheet(数据表) 6 Page - Fairchild Semiconductor

部件型号  FAN4803CP-1
说明  8-Pin PFC and PWM Controller Combo
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
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FAN4803CP-1 Datasheet(HTML) 6 Page - Fairchild Semiconductor

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FAN4803
PRODUCT SPECIFICATION
6
REV. 1.2.3 11/2/04
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 3 shows a leading
edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns OFF
and Switch 2 (SW2) turns ON at the same instant to mini-
mize the momentary “no-load” period, thus lowering ripple
voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method, substantially
reducing dissipation in the high-voltage PFC capacitor.
Typical Applications
One Pin Error Amp
The FAN4803 utilizes a one pin voltage error amplifier in the
PFC section (VEAO). The error amplifier is in reality a cur-
rent sink which forces 35µA through the output program-
ming resistor. The nominal voltage at the VEAO pin is 5V.
The VEAO voltage range is 4 to 6V. For a 11.3M
Ω resistor
chain to the boost output voltage and 5V steady state at the
VEAO, the boost output voltage would be 400V.
Programming Resistor Value
Equation 1 calculates the required programming resistor
value.
PFC Voltage Loop Compensation
The voltage-loop bandwidth must be set to less than 120Hz
to limit the amount of line current harmonic distortion.
A typical crossover frequency is 30Hz. Equation 1, for
simplicity, assumes that the pole capacitor dominates
the error amplifier gain at the loop unity-gain frequency.
Equation 2 places a pole at the crossover frequency,
providing 45 degrees of phase margin. Equation 3 places a
zero one decade prior to the pole. Bode plots showing the
overall gain and phase are shown in Figures 5 and 6. Figure 4
displays a simplified model of the voltage loop.
Rp
VV
I
V
A
M
BOOST
EAO
PGM
=
=
=
400
50V
35
113
.
.
µ
(1)
C
Pin
RV
VEAO
C
f)
COMP
p
BOOST
OUT
=
××
×
×
× ×
(2
2
π
(2)
C
W
COMP
300
11.3M
× 400V × 0.5V × 220µF × (2 × π × 30Hz)
F
2
16n
=
=
COMP
C
Figure 3. Typical Leading Edge Control Scheme.
REF
EA
+
+
OSC
DFF
R
D
Q
Q
CLK
U1
RAMP
CLK
U4
U3
C1
RL
I4
SW2
SW1
+
DC
I1
I2
I3
VIN
L1
VEAO
CMP
U2
RAMP
VEAO
TIME
VSW1
TIME




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