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EPM7256A 数据表(PDF) 21 Page - Altera Corporation |
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EPM7256A 数据表(HTML) 21 Page - Altera Corporation |
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21 / 64 page  Altera Corporation 21 MAX 7000A Programmable Logic Device Data Sheet Table 8. MAX 7000A JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO. The USERCODE instruction is available for MAX 7000AE devices only UESCODE These instructions select the user electronic signature (UESCODE) and allow the UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A and EPM7256A devices only. ISP Instructions These instructions are used when programming MAX 7000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam STAPL File, JBC File, or SVF File via an embedded processor or test equipment. |
类似零件编号 - EPM7256A |
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类似说明 - EPM7256A |
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