EPM7256A datasheet(43/64 Pages) ALTERA

部件名	EPM7256A

功能描述	Programmable Logic Device Family

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制造商	ALTERA [Altera Corporation]

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Altera Corporation

43

MAX 7000A Programmable Logic Device Data Sheet

Table 23. EPM7256AE External Timing Parameters

Note (1)

Symbol

Parameter

Conditions

Speed Grade

Unit

-5

-7

-10

Min

Max

Min

Max

Min

Max

tPD1

Input to non-

registered output

C1 = 35 pF

(2)

5.5

7.5

10

ns

tPD2

I/O input to non-

registered output

C1 = 35 pF

(2)

5.5

7.5

10

ns

tSU

Global clock setup

time

(2)

3.9

5.2

6.9

ns

tH

Global clock hold time (2)

0.0

ns

tFSU

Global clock setup

time of fast input

2.5

3.0

ns

tFH

Global clock hold time

of fast input

0.0

ns

tCO1

Global clock to output

delay

C1 = 35 pF

1.0

3.5

1.0

4.8

1.0

6.4

ns

tCH

Global clock high time

2.0

3.0

4.0

ns

tCL

Global clock low time

2.0

3.0

4.0

ns

tASU

Array clock setup time (2)

2.0

2.7

3.6

ns

tAH

Array clock hold time

(2)

0.2

0.3

0.5

ns

tACO1

Array clock to output

delay

C1 = 35 pF

(2)

1.0

5.4

1.0

7.3

1.0

9.7

ns

tACH

Array clock high time

2.0

3.0

4.0

ns

tACL

Array clock low time

2.0

3.0

4.0

ns

tCPPW

Minimum pulse width

for clear and preset

(3)

2.0

3.0

4.0

ns

tCNT

Minimum global clock

period

(2)

5.8

7.9

10.5

ns

fCNT

Maximum internal

global clock frequency

(2), (4)

172.4

126.6

95.2

MHz

tACNT

Minimum array clock

period

(2)

5.8

7.9

10.5

ns

fACNT

Maximum internal

array clock frequency

(2), (4)

172.4

126.6

95.2

MHz

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