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EPM7064LC84-7 数据表(PDF) 22 Page - Altera Corporation |
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EPM7064LC84-7 数据表(HTML) 22 Page - Altera Corporation |
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22 / 66 page  22 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet IEEE Std. 1149.1 (JTAG) Boundary-Scan Support MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990. Table 9 describes the JTAG instructions supported by the MAX 7000 family. The pin-out tables (see the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information) show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Table 9. MAX 7000 JTAG Instructions JTAG Instruction Devices Description SAMPLE/PRELOAD EPM7128S EPM7160S EPM7192S EPM7256S Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST EPM7128S EPM7160S EPM7192S EPM7256S Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. IDCODE EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. ISP Instructions EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S These instructions are used when programming MAX 7000S devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc), or Serial Vector Format file (.svf) via an embedded processor or test equipment. |
类似零件编号 - EPM7064LC84-7 |
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类似说明 - EPM7064LC84-7 |
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