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EPM7256AE 数据表(PDF) 34 Page - Altera Corporation |
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EPM7256AE 数据表(HTML) 34 Page - Altera Corporation |
34 / 64 page 34 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Tables 17 through 30 show EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing information. Table 17. EPM7032AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF (2) 4.5 7.5 10 ns tPD2 I/O input to non-registered output C1 = 35 pF (2) 4.5 7.5 10 ns tSU Global clock setup time (2) 2.9 4.7 6.3 ns tH Global clock hold time (2) 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 0.0 ns tCO1 Global clock to output delay C1 = 35 pF 1.0 3.0 1.0 5.0 1.0 6.7 ns tCH Global clock high time 2.0 3.0 4.0 ns tCL Global clock low time 2.0 3.0 4.0 ns tASU Array clock setup time (2) 1.6 2.5 3.6 ns tAH Array clock hold time (2) 0.3 0.5 0.5 ns tACO1 Array clock to output delay C1 = 35 pF (2) 1.04.3 1.07.2 1.0 9.4 ns tACH Array clock high time 2.0 3.0 4.0 ns tACL Array clock low time 2.0 3.0 4.0 ns tCPPW Minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns tCNT Minimum global clock period (2) 4.4 7.2 9.7 ns fCNT Maximum internal global clock frequency (2), (4) 227.3 138.9 103.1 MHz tACNT Minimum array clock period (2) 4.4 7.2 9.7 ns fACNT Maximum internal array clock frequency (2), (4) 227.3 138.9 103.1 MHz |
类似零件编号 - EPM7256AE |
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类似说明 - EPM7256AE |
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