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EPM7256AE 数据表(PDF) 32 Page - Altera Corporation |
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EPM7256AE 数据表(HTML) 32 Page - Altera Corporation |
32 / 64 page 32 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 11. MAX 7000A Timing Model The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 12 shows the timing relationship between internal and external delay parameters. f See Application Note 94 (Understanding MAX 7000 Timing) for more information. Logic Array Delay t LAD Output Delay t OD3 t OD2 t OD1 t XZ Z t X1 t ZX2 t ZX3 Input Delay t IN Register Delay t SU t H t PRE t CLR t RD t COMB t FSU t FH PIA Delay t PIA Shared Expander Delay t SEXP Register Control Delay t LAC t IC t EN I/O Delay t IO Global Control Delay t GLOB Internal Output Enable Delay t IOE Parallel Expander Delay t PEXP Fast Input Delay t FIN |
类似零件编号 - EPM7256AE |
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类似说明 - EPM7256AE |
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