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EPM7256AE 数据表(PDF) 23 Page - Altera Corporation |
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EPM7256AE 数据表(HTML) 23 Page - Altera Corporation |
23 / 64 page Altera Corporation 23 MAX 7000A Programmable Logic Device Data Sheet Figure 8 shows timing information for the JTAG signals. Figure 8. MAX 7000A JTAG Waveforms Table 11 shows the JTAG timing parameters and values for MAX 7000A devices. Note: (1) Timing parameters shown in this table apply for all specified VCCIO levels. Table 11. JTAG Timing Parameters & Values for MAX 7000A Devices Note (1) Symbol Parameter Min Max Unit tJCP TCK clock period 100 ns tJCH TCK clock high time 50 ns tJCL TCK clock low time 50 ns tJPSU JTAG port setup time 20 ns tJPH JTAG port hold time 45 ns tJPCO JTAG port clock to output 25 ns tJPZX JTAG port high impedance to valid output 25 ns tJPXZ JTAG port valid output to high impedance 25 ns tJSSU Capture register setup time 20 ns tJSH Capture register hold time 45 ns tJSCO Update register clock to output 25 ns tJSZX Update register high impedance to valid output 25 ns tJSXZ Update register valid output to high impedance 25 ns TDO TCK tJPZX t JPCO tJPH t JPXZ tJCP tJPSU t JCL tJCH TDI TMS Signal to Be Captured Signal to Be Driven t JSZX tJSSU tJSH t JSCO tJSXZ |
类似零件编号 - EPM7256AE |
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类似说明 - EPM7256AE |
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