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EPM7160E 数据表(PDF) 19 Page - Altera Corporation |
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EPM7160E 数据表(HTML) 19 Page - Altera Corporation |
19 / 66 page Altera Corporation 19 MAX 7000 Programmable Logic Device Family Data Sheet The programming times described in Tables 6 through 8 are associated with the worst-case method using the enhanced ISP algorithm. Tables 7 and 8 show the in-system programming and stand alone verification times for several common test clock frequencies. Table 6. MAX 7000S tPULSE & CycleTCK Values Device Programming Stand-Alone Verification tPPULSE (s) CyclePTCK tVPULSE (s) CycleVTCK EPM7032S 4.02 342,000 0.03 200,000 EPM7064S 4.50 504,000 0.03 308,000 EPM7128S 5.11 832,000 0.03 528,000 EPM7160S 5.35 1,001,000 0.03 640,000 EPM7192S 5.71 1,192,000 0.03 764,000 EPM7256S 6.43 1,603,000 0.03 1,024,000 Table 7. MAX 7000S In-System Programming Times for Different Test Clock Frequencies Device fTCK Units 10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz EPM7032S 4.06 4.09 4.19 4.36 4.71 5.73 7.44 10.86 s EPM7064S 4.55 4.60 4.76 5.01 5.51 7.02 9.54 14.58 s EPM7128S 5.19 5.27 5.52 5.94 6.77 9.27 13.43 21.75 s EPM7160S 5.45 5.55 5.85 6.35 7.35 10.35 15.36 25.37 s EPM7192S 5.83 5.95 6.30 6.90 8.09 11.67 17.63 29.55 s EPM7256S 6.59 6.75 7.23 8.03 9.64 14.45 22.46 38.49 s Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies Device fTCK Units 10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz EPM7032S 0.05 0.07 0.13 0.23 0.43 1.03 2.03 4.03 s EPM7064S 0.06 0.09 0.18 0.34 0.64 1.57 3.11 6.19 s EPM7128S 0.08 0.14 0.29 0.56 1.09 2.67 5.31 10.59 s EPM7160S 0.09 0.16 0.35 0.67 1.31 3.23 6.43 12.83 s EPM7192S 0.11 0.18 0.41 0.79 1.56 3.85 7.67 15.31 s EPM7256S 0.13 0.24 0.54 1.06 2.08 5.15 10.27 20.51 s |
类似零件编号 - EPM7160E |
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类似说明 - EPM7160E |
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