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EPM7064S 数据表(PDF) 18 Page - Altera Corporation |
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EPM7064S 数据表(HTML) 18 Page - Altera Corporation |
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18 / 66 page  18 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ A pulse time to erase, program, or read the EEPROM cells. ■ A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000S Device The time required to program a single MAX 7000S device in-system can be calculated from the following formula: where: tPROG = Programming time tPPULSE = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK =Number of TCK cycles to program a device fTCK = TCK frequency The ISP times for a stand-alone verification of a single MAX 7000S device can be calculated from the following formula: where: tVER =Verify time tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK =Number of TCK cycles to verify a device tPROG tPPULSE CyclePTCK fTCK -------------------------------- + = tVER tVPULSE CycleVTCK fTCK -------------------------------- + = |
类似零件编号 - EPM7064S |
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类似说明 - EPM7064S |
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