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EPM7128SQI160-10N 数据表(PDF) 28 Page - Altera Corporation |
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EPM7128SQI160-10N 数据表(HTML) 28 Page - Altera Corporation |
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28 / 66 page  28 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) VCC must rise monotonically. (5) The POR time for all 7000S devices does not exceed 300 μs. The sufficient VCCINT voltage level for POR is 4.5 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. (6) 3.3-V I/O operation is not available for 44-pin packages. (7) The VCCISP parameter applies only to MAX 7000S devices. (8) During in-system programming, the minimum DC input voltage is –0.3 V. (9) These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26. (10) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. (11) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL, PCI, or CMOS output current. (12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically –60 μA. (13) Capacitance is measured at 25° C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF. Figure 11 shows the typical output drive characteristics of MAX 7000 devices. Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices Timing Model MAX 7000 device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 12. MAX 7000 devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. The Altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation. VO Output Voltage (V) 12345 30 60 90 150 120 VCCIO = 3.3 V IOL IOH Room Temperature 3.3 VO Output Voltage (V) 12345 30 60 90 150 120 VCCIO = 5.0 V IOL IOH Room Temperature I O Typical Output Current (mA) I O Typical Output Current (mA) |
类似零件编号 - EPM7128SQI160-10N |
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类似说明 - EPM7128SQI160-10N |
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