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EPM7032S 数据表(PDF) 40 Page - Altera Corporation |
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EPM7032S 数据表(HTML) 40 Page - Altera Corporation |
40 / 66 page 40 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet fACNT Maximum internal array clock frequency (4) 175.4 142.9 116.3 100.0 MHz fMAX Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz Table 28. EPM7032S Internal Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -6 -7 -10 Min Max Min Max Min Max Min Max tIN Input pad and buffer delay 0.2 0.2 0.3 0.5 ns tIO I/O input pad and buffer delay 0.2 0.2 0.3 0.5 ns tFIN Fast input delay 2.2 2.1 2.5 1.0 ns tSEXP Shared expander delay 3.1 3.8 4.6 5.0 ns tPEXP Parallel expander delay 0.9 1.1 1.4 0.8 ns tLAD Logic array delay 2.6 3.3 4.0 5.0 ns tLAC Logic control array delay 2.5 3.3 4.0 5.0 ns tIOE Internal output enable delay 0.7 0.8 1.0 2.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 0.4 1.5 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 0.9 2.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 5.4 5.5 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns tSU Register setup time 0.8 1.0 1.3 2.0 ns tH Register hold time 1.7 2.0 2.5 3.0 ns tFSU Register setup time of fast input 1.9 1.8 1.7 3.0 ns tFH Register hold time of fast input 0.6 0.7 0.8 0.5 ns tRD Register delay 1.2 1.6 1.9 2.0 ns tCOMB Combinatorial delay 0.9 1.1 1.4 2.0 ns tIC Array clock delay 2.7 3.4 4.2 5.0 ns tEN Register enable time 2.6 3.3 4.0 5.0 ns tGLOB Global control delay 1.6 1.4 1.7 1.0 ns tPRE Register preset time 2.0 2.4 3.0 3.0 ns tCLR Register clear time 2.0 2.4 3.0 3.0 ns Table 27. EPM7032S External Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -6 -7 -10 MinMax MinMax MinMax MinMax |
类似零件编号 - EPM7032S |
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类似说明 - EPM7032S |
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