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EPF10K50V Datasheet(数据表) 43 Page - Altera Corporation

部件型号  EPF10K50V
说明  Embedded Programmable Logic Device Family
下载  128 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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EPF10K50V Datasheet(HTML) 43 Page - Altera Corporation

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Altera Corporation
43
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 18 shows the timing requirements for the JTAG signals.
Figure 18. JTAG Waveforms
Table 16 shows the timing parameters and values for FLEX 10K devices.
Table 16. JTAG Timing Parameters & Values
Symbol
Parameter
Min
Max
Unit
tJCP
TCK
clock period
100
ns
tJCH
TCK
clock high time
50
ns
tJCL
TCK
clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high-impedance to valid output
35
ns
tJSXZ
Update register valid output to high impedance
35
ns
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
tJSSU
tJSH
t
JSCO
tJSXZ




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