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EP3C80 数据表(PDF) 82 Page - Altera Corporation |
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EP3C80 数据表(HTML) 82 Page - Altera Corporation |
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82 / 274 page  5–22 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family Programmable Bandwidth Cyclone III Device Handbook July 2012 Altera Corporation Volume 1 ■ Figure 5–17 shows how the VCO frequency gradually decreases when the primary clock is lost and then increases as the VCO locks on to the secondary clock. After the VCO locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the VCO frequency. ■ Disable the system during switchover if the system is not tolerant to frequency variations during the PLL resynchronization period. You can use the clkbad[0] and clkbad[1] status signals to turn off the PFD (pfdena = 0) so the VCO maintains its last frequency. You can also use the switchover state machine to switch over to the secondary clock. Upon enabling the PFD, output clock enable signals (clkena) can disable clock outputs during the switchover and resynchronization period. After the lock indication is stable, the system can re-enable the output clock or clocks. Programmable Bandwidth The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its associated jitter. Cyclone III device family PLLs provide advanced control of the PLL bandwidth using the programmable characteristics of the PLL loop, including loop filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for open loop PLL response. Phase Shift Implementation Phase shift is used to implement a robust solution for clock delays in the Cyclone III device family. Phase shift is implemented with a combination of the VCO phase output and the counter starting time. The VCO phase output and counter starting time are the most accurate methods of inserting delays, because they are purely based on counter settings, which are independent of process, voltage, and temperature. You can phase shift the output clocks from the Cyclone III device family PLLs in either: ■ Fine resolution using VCO phase taps, or ■ Coarse resolution using counter starting time Figure 5–17. VCO Switchover Operating Frequency ΔFvco Primary Clock Stops Running Switchover Occurs VCO Tracks Secondary Clock Frequency Overshoot |
类似零件编号 - EP3C80 |
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类似说明 - EP3C80 |
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