CS4396

10

DS288PP1

SWITCHING CHARACTERISTICS - CONTROL PORT

10. Data must be held for sufficient time to bridge the transition time of CCLK.

Parameter

Symbol

Min

Max

Unit

SPI Mode

CCLK Clock Frequency

-6

MHz

RST Rising Edge to CS Falling

500

-

ns

CCLK Edge to CS Falling

(Note 9)

500

-

ns

CS High Time Between Transmissions

1.0

-

µs

CS Falling to CCLK Edge

20

-

ns

CCLK Low Time

66

-

ns

CCLK High Time

66

-

ns

CDIN to CCLK Rising Setup Time

40

-

ns

CCLK Rising to DATA Hold Time

(Note 10)

15

-

ns

Rise Time of CCLK and CDIN

(Note 11)

-100

ns

Fall Time of CCLK and CDIN

(Note 11)

-100

ns

CCLK Falling to CDOUT valid

45

ns

t r2

t f2

t dsu t dh

t sch

t scl

CS

CCLK

CDIN

t css

t csh

t spi

t srs

RST

Figure 3. SPI Control Port Timing