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CDB4341A 数据表(PDF) 9 Page - Cirrus Logic |
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CDB4341A 数据表(HTML) 9 Page - Cirrus Logic |
9 / 32 page CS4341A DS582PP1 9 3.5 De-Emphasis Control The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48 kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 5.2.3 for the desired de-emphasis control. NOTE: De-emphasis is only available in Single-Speed Mode. 3.6 Recommended Power-up Sequence 1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequences, as discussed in section 3.2. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will remain in a low power state with VQ low. 3. Load the desired register settings while keeping the PDN bit set to 1. 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximatel y 50µS when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description of power-up timing. LR C K SC L K Left C hanne l R ig h t C hanne l SD IN +3 +2 +1 +5 +4 MS B -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 LS B MS B LS B Figure 3. Left Justified up to 24-Bit Data L RCK SC L K Left C hann el SD IN -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 3 2 clo cks MSB R ight C h annel LSB MSB +1 +2 +3 +4 +5 LSB -6 -5 -4 -3 -2 -1 -7 MSB Figure 4. Right Justified Data Ga in dB -1 0d B 0dB F requenc y T2 = 15 µ s T1= 50 µ s F1 F2 3.183 kH z 10 .61 kH z Figure 5. De-Emphasis Curve |
类似零件编号 - CDB4341A |
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类似说明 - CDB4341A |
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