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CS4281-CM 数据表(PDF) 8 Page - Cirrus Logic |
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CS4281-CM 数据表(HTML) 8 Page - Cirrus Logic |
8 / 36 page 8 DS308PP4 CS4281 CrystalClear™ PCI Audio Interface CIRRUS LOGIC PRODUCT DATA SHEET EEPROM TIMING CHARACTERISTICS Note 4. (T A = 0 to 70 °C, PCIVDD = CVDD = VAUX = CRYVDD = 3.3 V; VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted) Notes: 18. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and the required external pull-up resistor. Parameter Symbol Min Max Units EECLK Low to EEDAT Data Out Valid tAA 07.0 µs Start Condition Hold Time tHD:STA 5.0 - µs EECLK Low tLEECLK 10 - µs EECLK High tHEECLK 10 - µs Start Condition Setup Time (for a Repeated Start Condition) tSU:STA 5.0 - µs EEDAT In Hold Time tHD:DAT 0- µs EEDAT In Setup Time tSU:DAT 250 - ns EEDAT/EECLK Rise Time (Note 18) tR -1 µs EEDAT/EECLK Fall Time tF - 300 ns Stop Condition Setup Time tSU:STO 5.0 - µs EEDAT Out Hold Time tDH 0- µs EECLK EEDAT (IN) EEDAT (OUT) t F t R t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO t AA t DH t HEECLK t LEECLK EEDAT (OUT) Figure 4. EEPROM Timing |
类似零件编号 - CS4281-CM |
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类似说明 - CS4281-CM |
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