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CS4235 数据表(PDF) 7 Page - Cirrus Logic |
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CS4235 数据表(HTML) 7 Page - Cirrus Logic |
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7 / 94 page  Timing Parameters (TA = 25 °C; VA, VD1, VDF1-VDF3 = +5 V; outputs loaded with 30 pF; Input Levels: Logic 0 = 0 V, Logic 1 = VDF, Rise/Fall time = 2 ns; Input/Output reference levels = 2.5 V) Parameter Symbol Min Max Units E 2PROM Timing (Note 1) SCL Low to SDA Data Out Valid tAA 03.5 µs Start Condition Hold Time tHD:STA 4.0 - µs Clock Low Period tLSCL 4.7 - µs Clock High Period tHSCL 4.0 - µs Start Condition Setup Time (for a Repeated Start Condition) tSU:STA 4.7 - µs Data In Hold Time tHD:DAT 0- µs Data In Setup Time tSU:DAT 250 - ns SDA and SCL Rise Time (Note 7) tR -1 µs SDA and SCL Fall Time tF - 300 ns Stop Condition Setup Time tSU:STO 4.7 - µs Data Out Hold Time tDH 0- ns Notes 7. Rise time on SDA is determined by the capacitance of the SDA line with all connected gates and the external pullup resistor required. SCL SDA (IN) SDA (OUT) tF tHSCL tLSCL tR t SU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tAA tDH E 2PROM 2-Wire Interface Timing CrystalClear Low Cost ISA Audio System TM CS4235 DS252PP2 7 |
类似零件编号 - CS4235 |
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类似说明 - CS4235 |
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