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CS22250 数据表(PDF) 7 Page - Cirrus Logic |
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CS22250 数据表(HTML) 7 Page - Cirrus Logic |
7 / 32 page CS22250 Wireless 10BT Controller 7 of 32 DS551PP2 Rev. 3.0 www.cirrus.com 3.2 Digital Wireless Radio Interface The CS22250 digital radio MAC I/F supports multiple radio baseband and RF interfaces. The baseband registers can be programmed during the configuration time using the control port interface. The MAC also provides the capability of programming the signal, service and length on a per packet basis without ARM intervention. This significantly improves the performance of the system. There are three primary digital interface ports for the CS22250 that are used for configuration and during normal operation. These ports are: • The Control Port, which is used to configure, set power consumption modes, write and/or read the status of the radio base band registers • The TX Port, which is used to output the data that needs to be transmitted from the network processor • The RX Port, which is used to input the received demodulated data to the network processor 3.3 FEC Codec The FEC codec performs Reed-Solomon code encoding to protect the data before it is transmitted to a noisy channel. It is a similar code as employed by the digital broadcast industry, such as ITU-T J.83 for DVB. The RS(255, 239) code implemented by the CS22250 can reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. The encoder/decoder can be programmed to vary the coding block length (N) and correctable error (t) to optimize the tradeoff between channel utilization and data protection. The range of N is currently set from 20 to 255, and the t is 8. The symbol size is fixed at 8 bits. Coding parameters can be set real time, allowing maximum flexibility for the system to adjust the FEC setting, such as block size, in order to optimize channel efficiency. The encoder also has a very low latency of two cycles. Both the encoder and decoder are fully pipelined in structure to achieve single cycle throughput. The FEC can be disabled in firmware. 3.4 High Speed Parallel Interface This optional connectivity interface is the extension of the ARM control bus brought outside of the CS22250 chip. In order to reduce the pin count, address and data are multiplexed in a 32-bit address/data External Control Bus. For ease of connecting other devices to the CS22250, this bus runs at half the speed of the internal ARM control bus. The external control Bus interface exchanges data with the main memory via DMAC (DMA controller block). This functional block supports two DMA engines for full duplex operation. Moreover, one external interrupt pin is supported. |
类似零件编号 - CS22250 |
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类似说明 - CS22250 |
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