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EG80C188EB25 数据表(PDF) 41 Page - InnovASIC, Inc |
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EG80C188EB25 数据表(HTML) 41 Page - InnovASIC, Inc |
41 / 85 page IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 41 of 85 1-888-824-4184 Table 8. IA188EB Pin/Signal Descriptions (Continued) Signal Pin Description Name PLCC LQFP PQFP test_n test_n 14 3 46 test. Input. Active Low. When the test_n input is high (i.e., not asserted), it causes the IA188EB to suspend operation during the execution of the WAIT instruction. Operation resumes when the pin is sampled low (asserted). txd0 txd0 52 39 2 Transmit (tx) data, Serial Port 0. Output. This pin is the serial data output for Serial Port 0. During synchronous serial communications, txd0 becomes the transmit clock (rxd0 functions as an output for data transmission). txd1 p2.1/txd1 58 45 8 Transmit (tx) data, Serial Port 1. Output. This pin is the serial data output for Serial Port 1. During synchronous serial communications, txd1 becomes the transmit clock (rxd1 functions as an output for data transmission). ucs_n ucs_n 30 18 61 upper chip select. Output. Active Low. This pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. vcc vcc 1, 23, 42, 64 11, 29, 50, 71 13, 34, 54, 72 Power (vcc). This pin provides power for the IA188EB device. It must be connected to a +5V DC power source. vss vss 2, 22, 43, 63, 65, 84 10, 30, 49, 51, 70, 72 12, 14, 33, 35, 53, 73 Ground (vss). This pin provides the digital ground (0V) for the IA188EB. It must be connected to a vss board plane. wr_n wr_n 5 74 37 write. Output. Active Low. When asserted (low), wr_n indicates that data available on the data bus are to be latched into the accessed memory or I/O device. |
类似零件编号 - EG80C188EB25 |
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类似说明 - EG80C188EB25 |
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