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AD7091R-8BRUZ 数据表(PDF) 11 Page - List of Unclassifed Manufacturers |
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AD7091R-8BRUZ 数据表(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 41 page AD7091R-2/AD7091R-4/AD7091R-8 Data Sheet Figure 7. 8-Channel Pin Configuration Table 7. 8-Channel Pin Function Descriptions Pin No. Mnemonic Description 1 CS Chip Select Input. When CS is held low, the serial bus enables and CS frames the output data on the SPI. 2 RESET Reset. Logic input. 3 VDD Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND. 4 REGCAP Decoupling Capacitor Pin For Voltage Output from Internal Regulator. Decouple this output pin separately to GND using a 2.2 μF capacitor. 5 REFIN/REFOUT Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended decoupling capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the internal reference with the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.0 V to VDD. 6, 19 GND Chip Ground. These pins are the ground reference point for all circuitry on the AD7091R-8. 7 MUXOUT Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to the ADCIN pin. 8 VIN0 Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF. 9 VIN2 Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF. 10 ALERT/BUSY/GPO0 Alert Output (ALERT). This is a multifunction pin determined by the configuration register. When functioning as ALERT, this pin is a logic output indicating that a conversion result has fallen outside the limit of the register settings. BUSY Output (BUSY). When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to indicate when a conversion is taking place. General-Purpose Digital Output (GPO0). The pin can also function as a general-purpose digital output. 11 VIN4 Analog Input 4. Single-ended analog input. The analog input range is 0 V to VREF. 12 VIN6 Analog Input 6. Single-ended analog input. The analog input range is 0 V to VREF. 13 VIN7 Analog Input 7. Single-ended analog input. The analog input range is 0 V to VREF. 14 VIN5 Analog Input 5. Single-ended analog input. The analog input range is 0 V to VREF. 15 GPO1 General-Purpose Digital Output. 16 VIN3 Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF. 17 VIN1 Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF. 18 ADCIN ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning network to the MUXOUT pin. 20 SDI Serial Data Input Bus. Data to be written to the on-chip control registers is provided on this input. Data is clocked into the registers on the falling edge of the SCLK input. Provide data MSB first. 21 SDO Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLK cycles are required to access the data. The data is provided MSB first. 22 SCLK Serial Clock. This pin acts as the serial clock input. 23 CONVST Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-and- hold mode into hold mode and initiates a conversion. 1 2 3 4 5 6 7 8 9 10 12 11 RESET VDD REGCAP MUXOUT GND CS VIN0 VIN2 VIN6 VIN4 ALERT/BUSY/GPO0 20 21 22 23 24 19 18 17 16 15 14 13 CONVST SCLK SDO ADCIN GND SDI VIN1 VIN3 VIN7 VIN5 GPO1 VDRIVE AD7091R-8 TOP VIEW (Not to Scale) REFIN/REFOUT Rev. 0 | Page 10 of 40 |
类似零件编号 - AD7091R-8BRUZ |
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类似说明 - AD7091R-8BRUZ |
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