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SN74LS95D 数据表(PDF) 4 Page - Motorola, Inc |
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SN74LS95D 数据表(HTML) 4 Page - Motorola, Inc |
4 / 6 page 5-174 FAST AND LS TTL DATA SN54/74LS95B DESCRIPTION OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recog- nized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recog- nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized. AC WAVEFORMS Figure 1 Figure 2 The shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V th(H) ts(H) ts(L) th(L) tW l/fmax tPHL tPLH *The Data Input is (DS for CP1) or (Pn for CP2). D CP1 or CP2 Q 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V ts(L) ts(H) th(L) ts(L) ts(H) ts(L) ts(H) th(H) tW th(L OR H) STABLE (H L ONLY) S CP1 CP2 tW 1.3 V 1.3 V 1.3 V 1.3 V (L H ONLY) (L H ONLY) |
类似零件编号 - SN74LS95D |
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类似说明 - SN74LS95D |
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