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CAT25C64U20A-TE13 数据表(PDF) 8 Page - Catalyst Semiconductor |
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CAT25C64U20A-TE13 数据表(HTML) 8 Page - Catalyst Semiconductor |
8 / 9 page 8 CAT25C32/64 Doc. No. 25087-00 8/99 SPI-1 Advanced Information Figure 7. WRSR Instruction Timing restriction is that the 64 bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C32/64 is automati- cally returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) in- struction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. Page Write The CAT25C32/64 features page write capability. After the first initial byte the host may continue to write up to 64 bytes of data to the CAT25C32/64. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only Figure 6. Write Instruction Timing Note: Dashed Line= mode (1, 1) – – – – Note: Dashed Line= mode (1, 1) — — — — SK SI SO 0 0 0 0 0 0 1 0 ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 012345678 21 22 23 24 25 26 27 28 29 30 31 CS OPCODE DATA IN HIGH IMPEDANCE 0 1 2 345 67 8 10 911 12 13 14 SCK SI MSB HIGH IMPEDANCE DATA IN 15 SO CS 7 6 5 4 3 2 10 00 0 00 0 0 1 OPCODE |
类似零件编号 - CAT25C64U20A-TE13 |
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类似说明 - CAT25C64U20A-TE13 |
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