8

CAT25C03/05/09/17/33

Doc. No. 25068-00 2/98

Advanced

Figure 7. WRSR Timing

Figure 6. Write Instruction Timing

SK

SI

CS

SO

0

0

0

0

0

0

1

0

ADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

012345678

21

22

23

24

25

26

27

28

29

30

31

reaches the end of the page and clock continues, the

counter will “roll over” to the first address of the page and

overwrite any data that may have been written. The

CAT25C03/05/09/17/33 is automatically returned to the

write disable state at the completion of the write cycle.

Figure 8 illustrates the page write sequence.

To write to the status register, the WRSR instruction

should be sent.

Figure 7 illustrates the sequence of

writing to status register.

Page Write

The CAT25C03/05/09/17/33 features page write capa-

bility. After the initial byte, the host may continue to write

up to 16 bytes of data to the CAT25C03/05 and 32 bytes

of data for 25C09/17/33. After each byte of data re-

ceived, lower order address bits are internally

incremented by one; the high order bits of address

willremain constant.The only restriction is that the X

(X=16 for 25C03/05 and X=32 for 25C09/17/33) bytes

must reside on the same page. If the address counter

0

1

2

345

67

8

10

911

12

13

14

6

74

53

2

1

0

CS

SCK

SI

SO

INSTRUCTION

DATA IN

15