TPA3117D2

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SLOS672 – OCTOBER 2010

PIN FUNCTIONS

PIN

I/O/P

DESCRIPTION

NAME

NUMBER

LINN

1

I

Negative audio input for left channel. Biased at 3V.

GAIN0

2

I

Gain select least significant bit. TTL logic levels with compliance to AVCC.

GAIN1

3

I

Gain select most significant bit. TTL logic levels with compliance to AVCC.

AVCC

4

P

Analog supply

AGND

5

Analog signal ground. Connect to the thermal pad.

REG_OUT

6

O

5V regulated output. Connect 2.2µF to AGND after the series 10

Ω resistor.

Power limit level adjust. Connect a resistor divider from REG_OUT to AGND to set power limit.

PLIMIT

7

I

Connect directly to REG_OUT for no power limit.

RINN

8

I

Negative audio input for right channel. Biased at 3V.

RINP

9

I

Positive audio input for right channel. Biased at 3V.

10, 12, 13,

NC

Not connected

28, 29

PBTL

11

I

Parallel BTL mode switch (low = BTL mode, high = PBTL mode)

Power supply for right channel H-bridge. Right channel and left channel power supply inputs are

PVCCR

14, 15

P

connected internally. PVCCR and PVCCL must be connected together on the PCB.

BSPR

16

I

Bootstrap I/O for right channel, positive high-side FET.

OUTPR

17

O

Class-D H-bridge positive output for right channel.

PGND

18

Power ground for the H-bridges.

OUTNR

19

O

Class-D H-bridge negative output for right channel.

BSNR

20

I

Bootstrap I/O for right channel, negative high-side FET.

BSNL

21

I

Bootstrap I/O for left channel, negative high-side FET.

OUTNL

22

O

Class-D H-bridge negative output for left channel.

PGND

23

Power ground for the H-bridges.

OUTPL

24

O

Class-D H-bridge positive output for left channel.

BSPL

25

I

Bootstrap I/O for left channel, positive high-side FET.

Power supply for left channel H-bridge. Right channel and left channel power supply inputs are

PVCCL

26, 27

P

connected internally. PVCCR and PVCCL must be connected together on the PCB.

Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels

SD

30

I

with compliance to AVCC.

FSEL

31

I

Frequency select input pin (low = 300kHz, high = 400kHz)

LINP

32

I

Positive audio input for left channel. Biased at 3V.

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