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AD5686BRUZ 数据表(PDF) 1 Page - Analog Devices |
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AD5686BRUZ 数据表(HTML) 1 Page - Analog Devices |
1 / 28 page Quad, 16-/12-Bit nanoDAC+ with SPI Interface Data Sheet AD5686/AD5684 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES High relative accuracy (INL): ±2 LSB maximum @ 16 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Robust 4 kV HBM and 1.5 kV FICDM ESD rating Low power: 1.8 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range APPLICATIONS Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD5686/AD5684, members of the nanoDAC+™ family, are low power, quad, 16-/12-bit buffered voltage output DACs. The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. The AD5686/AD5684 also incorporate a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode. The AD5686/AD5684 employ a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Table 1. Quad nanoDAC+ Devices Interface Reference 16-Bit 14-Bit 12-Bit SPI Internal AD5686R AD5685R AD5684R SPI External AD5686 AD5684 I2C Internal AD5696R AD5695R AD5694R I2C External AD5696 AD5694 PRODUCT HIGHLIGHTS 1. High Relative Accuracy (INL). AD5686 (16-bit): ±2 LSB maximum AD5684 (12-bit): ±1 LSB maximum 2. Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum 3. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP SCLK VLOGIC SYNC SDIN SDO INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD VREF GND VDD POWER- DOWN LOGIC POWER-ON RESET GAIN ×1/×2 RSTSEL GAIN LDAC RESET AD5686/AD5684 |
类似零件编号 - AD5686BRUZ |
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类似说明 - AD5686BRUZ |
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