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EPM7160E 数据表(PDF) 24 Page - Altera Corporation |
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EPM7160E 数据表(HTML) 24 Page - Altera Corporation |
24 / 66 page 24 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms Table 12 shows the JTAG timing parameters and values for MAX 7000S devices. f For more information, see Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices Symbol Parameter Min Max Unit tJCP TCK clock period 100 ns tJCH TCK clock high time 50 ns tJCL TCK clock low time 50 ns tJPSU JTAG port setup time 20 ns tJPH JTAG port hold time 45 ns tJPCO JTAG port clock to output 25 ns tJPZX JTAG port high impedance to valid output 25 ns tJPXZ JTAG port valid output to high impedance 25 ns tJSSU Capture register setup time 20 ns tJSH Capture register hold time 45 ns tJSCO Update register clock to output 25 ns tJSZX Update register high impedance to valid output 25 ns tJSXZ Update register valid output to high impedance 25 ns TDO TCK tJPZX t JPCO tJPH t JPXZ tJCP tJPSU t JCL tJCH TDI TMS Signal to Be Captured Signal to Be Driven t JSZX tJSSU tJSH t JSCO tJSXZ |
类似零件编号 - EPM7160E |
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类似说明 - EPM7160E |
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