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EPM7256AEFC256-7 数据表(PDF) 46 Page - Altera Corporation

部件名 EPM7256AEFC256-7
功能描述  Programmable Logic Device
Download  64 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM7256AEFC256-7 数据表(HTML) 46 Page - Altera Corporation

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Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Table 25. EPM7512AE External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-12
Min
Max
Min
Max
Min
Max
tPD1
Input to non-
registered output
C1 = 35 pF
(2)
7.5
10.0
12.0
ns
tPD2
I/O input to non-
registered output
C1 = 35 pF
(2)
7.5
10.0
12.0
ns
tSU
Global clock setup
time
(2)
5.6
7.6
9.1
ns
tH
Global clock hold time (2)
0.0
0.0
0.0
ns
tFSU
Global clock setup
time of fast input
3.0
3.0
3.0
ns
tFH
Global clock hold time
of fast input
0.0
0.0
0.0
ns
tCO1
Global clock to output
delay
C1 = 35 pF
1.0
4.7
1.0
6.3
1.0
7.5
ns
tCH
Global clock high time
3.0
4.0
5.0
ns
tCL
Global clock low time
3.0
4.0
5.0
ns
tASU
Array clock setup time (2)
2.5
3.5
4.1
ns
tAH
Array clock hold time
(2)
0.2
0.3
0.4
ns
tACO1
Array clock to output
delay
C1 = 35 pF
(2)
1.0
7.8
1.0
10.4
1.0
12.5
ns
tACH
Array clock high time
3.0
4.0
5.0
ns
tACL
Array clock low time
3.0
4.0
5.0
ns
tCPPW
Minimum pulse width
for clear and preset
(3)
3.0
4.0
5.0
ns
tCNT
Minimum global clock
period
(2)
8.6
11.5
13.9
ns
fCNT
Maximum internal
global clock frequency
(2), (4)
116.3
87.0
71.9
MHz
tACNT
Minimum array clock
period
(2)
8.6
11.5
13.9
ns
fACNT
Maximum internal
array clock frequency
(2), (4)
116.3
87.0
71.9
MHz


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