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VSP2210 Datasheet(数据表) 2 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
部件型号  VSP2210
说明  CCD SIGNAL PROCESSOR For Digital Cameras
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制造商  BURR-BROWN [Burr-Brown (TI)]
网页  http://www.burr-brown.com
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VSP2210 Datasheet(HTML) 2 Page - Burr-Brown (TI)

 
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®
VSP2210
SPECIFICATIONS
At TA = full specified temperature range, VCC = +3.0V, DRVDD = +3.0V, conversion rate (fADDCK) = 20MHz, unless otherwise specified.
VSP2210Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
10
Bits
MAXIMUM CONVERSION RATE
20
MHz
DIGITAL INPUT
Logic Family
TTL
Input Voltage
LOW to HIGH Threshold Voltage (VT+)
1.7
V
HIGH to LOW Threshold Voltage (VT–)
1.0
V
Input Current
Logic HIGH (IIH), VIN = +3V
±20
µA
Logic LOW (IIL), VIN = 0V
±20
µA
ADCCK Clock Duty Cycle
50
%
Input Capacitance
5pF
Maximum Input Voltage
–0.3
5.3
V
DIGITAL OUTPUT
Logic Family
CMOS
Logic Coding
Straight Binary
Output Voltage
Logic HIGH (VOH), IOH = –2mA
2.4
V
Logic LOW (VOL), IOL = 2mA
0.4
V
ANALOG INPUT (CCDIN)
Input Signal Level for Full-Scale Out
PGA Gain = 0dB
900
mV
Input Capacitance
15
pF
Input Limit
–0.3
3.3
V
TRANSFER CHARACTERISTICS
Differential Non-Linearity (DNL)
PGA Gain = 0dB
±0.5
LSB
Integral Non-Linearity (INL)
PGA Gain = 0dB
±1
LSB
No Missing Codes
Guaranteed
Step Response Settling Time
Full-Scale Step Input
1
Pixels
Overload Recovery Time
Step Input from 1.8V to 0V
2
Pixels
Data Latency
9 (fixed)
Clock Cycles
Signal-to-Noise Ratio(1)
Grounded Input Cap, PGA Gain = 0dB
79
dB
Grounded Input Cap, Gain = +24dB
55
dB
CCD Offset Correction Range
–180
200
mV
CDS
Reference Sample Settling Time
Within 1 LSB, Driver Impedance = 50
11
ns
Data Sample Settling Time
Within 1 LSB, Driver Impedance = 50
11
ns
INPUT CLAMP
Clamp-On Resistance
400
Clamp Level
1.5
V
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Gain Control Resolution
10
Bits
Maximum Gain
Gain Code = 1111111111
42
dB
High Gain
Gain Code = 1101001000
34
dB
Medium Gain
Gain Code = 1000100000
20
dB
Low Gain
Gain Code = 0010000000
0
dB
Minimum Gain
Gain Code = 0000000000
–6
dB
Gain Control Error
±0.5
dB
OPTICAL BLACK CLAMP LOOP
Control DAC Resolution
10
Bits
Optical Black Clamp Level
Programmable Range of Clamp Level
0
60
LSB
OBCLP Level at CODE = 1000
32
LSB
Minimum Output Current for Control DAC
COB Pin
±0.15
µA
Maximum Output Current for Control DAC
COB Pin
±153
µA
Loop Time Constant
C
COB = 0.1µF
40.7
µs
Slew Rate
CCOB = 0.1µF, Output Current from
1530
V/s
Control DAC is Saturated
GENERAL-PURPOSE 8-BIT DAC (DAC0, DAC1)
Minimum Output Voltage
Input Code = 00000000
0.1
V
Maximum Output Voltage
Input Code = 11111111
2.9
V
Differential Non-Linearity (DNL)
At Input Code = 16 to 224
±0.25
LSB
Integral Non-Linearity (INL)
At Input Code = 16 to 192
±1
LSB
Offset Error
±200
mV
Gain Error
±5%
Monotonicity
Guaranteed
NOTE: (1) SNR = 20 log (full-scale voltage/rms noise).




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